1. Field of the Invention
This invention relates generally to Josephson tunneling interferometer devices which have application as logic devices in Josephson tunneling circuits. More specifically it relates to Josephson tunneling interferometer devices which, in contrast to a simple junction, are capable of operating with high current gains at low operating currents and have a threshold characteristic with large lobe separation. This latter feature either maintains or increases the operating margins of the resulting logic devices. Still more specifically, it relates to a Josephson junction interferometer device which contains more than two junctions; preferably three, wherein the maximum Josephson current, I.sub.m, is greater and preferably twice as large in the center one of three junctions than the maximum Josephson current in the remaining junctions. In a preferred arrangement, gate current is fed into the interferometer device in a symmetrical manner such that the gate current is applied at the center of an inductance L disposed between the center junction and the outer junctions via inductances which have a value of inductance which can be three times the value of the inductance, L. Because there are such a large number of arrangements which include a plurality of junctions, an equally large number of current feed arrangements are required which can be encompassed by adhering to the following criterion: The current should be fed in so that, with zero control field, the phase difference, .phi., across the junctions is the same (.pi./2) just prior to switching, that is, all junctions in the interferometer switch simultaneously. While three or more junctions can be utilized to form an interferometer having the desired operating margins and current gains, the small size of the three junction interferometer is most attractive from a practical standpoint. The fact that the interferometer devices of the present application can be operated in both latching and non-latching modes permits them to be utilized in a wide variety of circuit applications.
2. Description of the Prior Art
Josephson junction devices are well known in the prior art for use as both memory devices and as switching devices for use in ultra-high speed logic circuits. The characteristics of a typical Josephson device is described in detail in a publication entitled "The Tunneling Cryotron -- A Superconductive Logic Element Based on Electron Tunneling" by J. Matisoo which appeared in the Proceedings of the IEEE, February 1967, Vol.55, No.2, pp.172-180. A typical logic device of the character described in the article consists of a gate and a control line which are positioned above but insulated from the gate. The control line is generally made of a superconductor such as niobium, tin or lead. The Josephson junction device itself consists of two strips of superconducting material which overlap. In the region of the overlap, the two strips of superconductive material are separated from each other by a tunnel barrier which may be formed of an oxide of one of the superconductor strips. The oxide barrier usually has a thickness of the order of 10-30 angstroms. The gate and control line are normally placed on a superconducting ground plane and insulated from it.
Gate current, I.sub.g, is fed through the junction which, being in the zero voltage state, shorts an output impedance, Z.sub.o. If the linear sum of the input currents, I.sub.c, reduces the Josephson threshold current, I.sub.m, below I.sub.g, the current switches to a voltage equal to or less than 2.DELTA./e (2.DELTA./e = 2.5mV for lead junctions). After switching, the voltage V.sub.g produces a current I.sub.r equal to V.sub.g /Z.sub.o in the output impedance. The resulting current may be utilized to control other circuits. In most instances, the switched junction remains locked in the voltage state and must be reset to the zero voltage state by a momentary decrease in I.sub.g. However, d.c. powered non-latching circuits have been proposed by W. Baechtold, Digest of Technical Papers, I.S.S.C.C., Philadelphia, 146(1975).
Quantum interference between two parallel Josephson junctions, also called interferometers, has been described by R. C. Jaklevic, J. Lambe, J. E. Mercereau, A. H. Silver, Physical Review, 140, A1628, November 1965.
IBM Technical Disclosure Bulletin, Vol.17, No.3, August 1974, pp.901-902, in an article entitled "Single Flux Quantum Memory Cell for NDRO" by W. W. Jutzi shows a center fed triple junction interferometer wherein all the junctions are of the same size and carry the same currents. In this arrangement, however, the effort was directed not to increasing the separation between lobes but rather to having a region of overlap where three energy states are possible. The TDB arrangement is really not concerned with devices that switch to the voltage state nor is it concerned with having a large operating range for devices with high gain.
An article entitled "Three Junction Interferometer" by Stuelm and Wilmsen, in Applied Physics Letters, Vol.20, No.11, June 1972, pp.458-460, shows an asymmetrically fed triple Josephson junction arrangement in which all the junctions are the same size. This article apparently recognizes that the spacing between the lobes of a Josephson junction threshold curve may be increased by adding an additional junction to the known two junction interferometer. However, while it increases magnetic field sensitivity over the known two junction interferometer, this asymmetrically fed three Josephson junction interferometer does not have the maximum Josephson zero voltage current through it at zero applied magnetic field. The article, however, does indicate that zero applied magnetic field coincides with the maximum current through the interferometer for a symmetrically fed device similar to that shown in the IBM Technical Disclosure Bulletin. Thus, while it has been recognized that the magnetic field sensitivity can be improved in both the two and three junction interferometers, all of these arrangements are concerned with enhancing the aforementioned magnetic field sensitivity and not with achieving high current gains while simultaneously improving the operating margins of devices which are to be used in the logic environment.